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| Freescale Semiconductor Advance Information Document Number: MM908E624 Rev. 8.0, 3/2007 Integrated Triple High-Side Switch with Embedded MCU and LIN Serial Communication for Relay Drivers The 908E624 is an integrated single-package solution that includes a high-performance HC08 microcontroller with a SMARTMOSTM analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), an analog-to-digital converter (ADC), serial peripheral interface (SPI) (only internal), and an internal clock generator module. The analog control die provides three high-side outputs with diagnostic functions, voltage regulator, watchdog, current sense operational amplifier, and local interconnect network (LIN) physical layer. The single-package solution, together with LIN, provides optimal application performance adjustments and space-saving PCB design. It is well suited for the control of automotive high-current motors applications using relays (e.g., window lifts, fans, and sun roofs). Features * High-Performance M68HC908EY16 Core * 16 K Bytes of On-Chip Flash Memory, 512 Bytes of RAM * Internal Clock Generator Module * Two 16-Bit, 2-Channel Timers * 10-Bit Analog-to-Digital Converter (ADC) * LIN Physical Layer Interface * Low Dropout Voltage Regulator * Three High-Side Outputs * Two Wake-Up Inputs * 16 Microcontroller I / Os * Pb-Free Packaging Designated by Suffix Code EW VBAT 908E624 HIGH-SIDE SWITCH DWB SUFFIX EW (Pb-FREE) SUFFIX 98ASA99294D 54-TERMINAL SOICW ORDERING INFORMATION Device MM908E624ACDWB/ R2 *MM908E624ACEW/ R2 *MM908E624AYEW/ R2 Temperature Range (TA) - 40C to 85C - 40C to 125C Package 54 SOICW Notes* Recommended for new designs 908E624 LIN Interface VSUP1 +5.0 V LIN VREFH VDDA EVDD VCC VDD VREFL VSSA EVSS AGND GND RXD PTE1/RXD RST RST_A IRQ IRQ_A PTD0/TACH0 PWMIN Microcontroller Ports PTA0-4 PTB1; 3-7 PTC2-4 PTD1/TACH1 OUT -E WDCONF HS2 +E VSUP2 HS3 L1 L2 HS1 M To Microcontroller A/D Channel Figure 1. 908E624 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2006. All rights reserved. Internal Bus PTA1/KBD1 PTA0/KBD0 PTD1/TACH1 PTD1/TACH1 PTB7/AD7/TBCH1 PTD0/TACH0 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTE1/RxD PTB2/AD2 PTB1/AD1 PTB0/AD0 PTE0/TxD PORT A PTA2/KBD2 PTC0/MISO DDRA PORT C PTC4/OSC1 PTA3/KBD3 PTC1/MOSI DDRC DDRD PORT D PORT B DDRB DDRE PORT E 2 RST_A IRQ_A PTE1/RXD PTD0/TACH0 IRQ VREFL AGND VSUP1 VSUP2 EVDD RXD EVSS VSSA GND LIN PWMIN WDCONF RST 908E624 M68HC08 CPU VSUP1 ALU 5-Bit Keyboard Interrupt Module Single Breakpoint Break Module INTERNAL BLOCK DIAGRAM VREFH PTE0/TXD Voltage Regulator TXD LIN Physical Layer Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes Monitor ROM, 310 Bytes 2-channel Timer Interface Module B 2-channel Timer Interface Module A VDDA CPU Registers PTA0/KBD0 VDD PTA1/KBD1 Window Watchdog PWMIN PTA2/KBD2 FLASH programming (burn in) ROM, 1024 Bytes VSUP2 User Flash Vector Space, 36 Bytes Enhanced Serial Communication Interface Module Computer Operating Properly Module PTA3/KBD3 Internal Clock Generator Module High Side Driver & Diagnostic VSUP2 PWMIN HS1 OSC2 OSC1 PTA4/KBD4 Reset Control Module PTB1/AD1 24 Internal System Integration Module Serial Pheripheral Interface Module RST High Side Driver & Diagnostic HS2 PTB3/AD3 Single External IRQ Module Configuration Register Module IRQ VSUP2 PTB4/AD4 10 Bit Analog-to-Digital Converter Module Periodic Wakeup Timebase Module VREFH VDDA VREFL High Side Driver & Diagnostic PTA6/SS SS HS3 PTB5/AD5 VSSA PTB6/AD6/TBCH0 POWER Arbiter Module VDD VSS PTC0/MISO MISO Wake Up Input 1 MOSI L1 PTB7/AD7/TBCH1 Power-On Reset Module Prescaler Module INTERNAL BLOCK DIAGRAM PTC1/MOSI SPI & Mode Control PTC2/MCLK Security Module BEMF Module PTA5/SPSCK PTA6/SS PTA5/SPSCK PTA4/KBD4 PTC2/MCLK PTC3/OSC2 PTC4/OSC1 SPSCK Wake Up Input 2 L2 PTC3/OSC2 VCC +E Amplifier -E FLSVPP OUT MCU Die Analog Die Analog Integrated Circuit Device Data Freescale Semiconductor Figure 2. 908E624 Simplified Internal Block Diagram TERMINAL CONNECTIONS TERMINAL CONNECTIONS PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST PTB1/AD1 PTD0/TACH0 PTD1/TACH1 NC NC NC PWMIN RST_A IRQ_A NC NC NC L1 L2 HS3 HS2 HS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD NC RXD WDCONF +E -E OUT VCC AGND VDD NC VSUP1 GND LIN VSUP2 Figure 3. Terminal Connections Table 1. Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 18. Die MCU Terminal 1 2 6 7 8 11 3 4 5 9 10 12 13 14, 15, 16, 20, 21, 22, 32, 41 42 Terminal Name PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK IRQ RST PTD0/TACH0 PTD1/TACH1 NC Formal Name Port B I/Os Definition These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU Port C I/Os These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. This terminal is an asynchronous external interrupt input terminal. This terminal is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. These terminals are special-function, bidirectional I /O port terminals that are shared with other functional modules in the MCU. Not connected. MCU MCU MCU -- External Interrupt Input External Reset Port D I /Os No Connect MCU PTE1/ RXD Port E I /O This terminal is a special-function, bidirectional I/O port terminal that can is shared with other functional modules in the MCU. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 3 TERMINAL CONNECTIONS Table 1. Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 18. Die MCU MCU MCU MCU Terminal 43 48 44 47 45 46 49 50 52 53 54 51 17 18 19 23 24 25 26 27 31 28 29 30 34 33 35 36 37 38 39 Terminal Name VREFL VREFH VSSA VDDA EVSS EVDD PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 FLSVPP PWMIN RST_A IRQ_A L1 L2 HS3 HS2 HS1 VSUP1 VSUP2 LIN GND AGND VDD VCC OUT -E +E WDCONF Formal Name ADC References ADC Supply Terminals MCU Power Supply Terminals Port A I /Os Definition These terminals are the reference voltage terminals for the analog-todigital converter (ADC). These terminals are the power supply terminals for the analog-to-digital converter. These terminals are the ground and power supply terminals, respectively. The MCU operates from a single-power supply. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU Analog Analog Analog Analog Analog Test Terminal Direct High-Side Control Input Internal Reset Output Internal Interrupt Output Wake-Up Inputs High-Side Output For test purposes only. Do not connect in the application. This terminal allows the enabling and PWM control of the high-side HS1 and HS2 terminals. This terminal is the reset output terminal of the analog die. This terminal is the interrupt output terminal of the analog die indicating errors or wake-up events. These terminals are the wake-up inputs of the analog chip. These output terminals are low RDS(ON) high-side switches. Analog Analog Analog Analog Analog Analog Analog Analog Power Supply Terminals LIN Bus Power Ground Terminals Voltage Regulator Output Amplifier Power Supply Amplifier Output Amplifier Inputs Window Watchdog Configuration Terminal LIN Transceiver Output These terminals are device power supply terminals. This terminal represents the single-wire bus transmitter and receiver. These terminals are device power ground connections. The + 5.0 V voltage regulator output terminal is intended to supply the embedded microcontroller. This terminal is the single +5.0 V power supply for the current sense operational amplifier. This terminal is the output of the current sense operational amplifier. These terminals are the current sense operational amplifier inverted and non-inverted inputs. This input terminal is for configuration of the watchdog period and allows the disabling of the watchdog. Analog 40 RXD This terminal is the output of LIN transceiver. 908E624 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device. Rating ELECTRICAL RATINGS Supply Voltage Analog Chip Supply Voltage under Normal Operation (Steady-State) Analog Chip Supply Voltage under Transient Conditions MCU Chip Supply Voltage Input Terminal Voltage Analog Chip Microcontroller Chip Maximum Microcontroller Current per Terminal All Terminals except VDD, VSS, PTA0:PTA6 , PTC0:PTC1 PTA0:PTA6, PTC0:PTC1 Terminals Maximum Microcontroller VSS Output Current Maximum Microcontroller VDD Input Current Current Sense Operational Amplifier Maximum Input Voltage, +E, -E Terminals Maximum Input Current, +E, -E Terminals Maximum Output Voltage, OUT Terminal Maximum Output Current, OUT Terminal LIN Supply Voltage Normal Operation (Steady-State) Transient Input Voltage (per ISO7637 Specification) and with External Components (Figure 4, page 15) L1 and L2 Terminal Voltage Normal Operation with a 33 k resistor (Steady-State) Transient Input Voltage (per ISO7637 Specification) and with External Components (Figure 4, page 15) ESD Voltage Human Body Model Machine Model (1) Charge Device Model (1) (1) Symbol Value Unit V VSUP(SS) VSUP(PK) VDD - 0.3 to 27 - 0.3 to 40 - 0.3 to 5.5 V VIN (ANALOG) VIN (MCU) - 0.3 to VDD +0.3 VSS - 0.3 to VDD +0.3 mA IPIN(1) IPIN(2) IMVSS IMVDD 15 25 100 100 mA mA V + E-E I + E-E VOUT IOUT - 0.3 to 7.0 20 - 0.3 to VCC + 0.3 20 V mA V mA V VBUS(SS) VBUS(PK) -18 to 40 -150 to 100 V VWAKE(SS) VWAKE(PK) -18 to 40 -100 to 100 V VESD1 VESD2 VESD3 2000 100 500 Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model, Robotic (CZAP = 4.0 pF). 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device. Rating THERMAL RATINGS Package Operating Ambient Temperature (4) MM908E624ACDWB and MM908E624ACEW MM908E624AYEW Operating Junction Temperature (2)(4) MM908E624ACDWB and MM908E624ACEW MM908E624AYEW Storage Temperature Peak Package Reflow Temperature During Solder Mounting (3) DWB Suffix EW (Pb-Free) Suffix TSTG TSOLDER 245 260 TJ TA - 40 to 85 - 40 to 125 C - 40 to 125 - 40 to 125 - 40 to 150 C C C Symbol Value Unit Notes 2. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because of higher power dissipation of the analog die. The analog die junction temperature must not exceed 150C under these conditions. 3. Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 4. Independent of TA, device parametrics are only guaranteed for - 40 < TJ < 125C . Please see note 2. TJ is a factor of power dissipation, package thermal resistance, and available heat sinking. 908E624 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, - 40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic SUPPLY VOLTAGE RANGE Nominal Operating Voltage Functional Operating Voltage SUPPLY CURRENT RANGE Normal Mode (6) VSUP = 13.5 V, Analog Chip in Normal Mode, MCU Operating Using Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled Stop Mode (6), (7) Sleep Mode (6), (7) VSUP = 13.5 V, LIN in recessive state VSUP = 13.5 V, LIN in recessive state DIGITAL INTERFACE RATINGS (ANALOG DIE) Output Terminal RST_A Low-State Output Voltage (IOUT = - 1.5 mA) High-State Output Current (VOUT > 3.5 V) Pulldown Current Limitation Output Terminal IRQ_A Low-State Output Voltage (IOUT = - 1.5 mA) High-State Output Voltage (IOUT = 250 A) Output Terminal RXD Low-State Output Voltage (IOUT = - 1.5 mA) High-State Output Voltage (IOUT = 250 A) Capacitance (8) (5) Symbol Min Typ Max Unit VSUP VSUPOP 5.5 -- -- -- 18 27 V V IRUN ISTOP ISLEEP -- -- -- 20 60 35 -- 75 45 mA A A VOL IOH IOL_MAX -- -- -1.5 -- 250 -- 0.4 -- -8.0 V A mA V VOL VOH -- 3.85 -- -- 0.4 -- VOL VOH CIN -- 3.85 -- -- -- 4.0 0.4 -- -- V V pF Input Terminal PWMIN Input Logic Low Voltage Input Logic High Voltage Input Current Capacitance (8) Terminal TXD, SS - Pullup Current VIL VIH IIN CIN IPU -- 3.5 -10 -- -- -- -- -- 4.0 40 1.5 -- 10 -- -- V V A pF A Notes 5. Device is fully functional. All functions are operating. Overtemperature may occur. 6. Total current (IVSUP1 + IVSUP2) measured at GND terminal. 7. 8. Stop and Sleep mode current will increase if VSUP exceeds 15 V. This parameter is guaranteed by process monitoring but is not production tested. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, - 40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic SYSTEM RESETS AND INTERRUPTS Low-Voltage Reset (LVR) Threshold Low-Voltage Interrupt (LVI) Threshold Hysteresis High-Voltage Interrupt (HVI) Threshold Hysteresis VOLTAGE REGULATOR (9) Normal Mode Output Voltage 2.0 mA < IDD < 50 mA, 5.5 V < VSUP < 27 V Normal Mode Output Current Limitation Dropout Voltage VSUP = 4.9 V, IDD = 50 mA Stop Mode Output Voltage (11) Stop Mode Regulator Current Limitation Line Regulation Normal Mode, 5.5 V < VSUP < 27 V, IDD = 10 mA Stop Mode, 5.5 V < VSUP < 27 V, IDD = 2.0 mA Load Regulation Normal Mode, 1.0 mA < IDD < 50 mA, VSUP = 18 V Stop Mode, 1.0 mA < IDD < 5.0 mA, VSUP = 18 V Overtemperature Pre-Warning (Junction) (12) Thermal Shutdown Temperature (Junction) Temperature Threshold Difference TSD - TPRE (12) (10) Symbol Min Typ Max Unit V LVRON 3.6 4.0 4.4 V V V LVI V LVI_HYS 5.7 -- 6.0 1.0 6.6 -- V HVI V HVI_HYS 18 -- 19.25 220 20.5 -- V mV V DDRUN 4.75 IDDRUN V DDDROP -- V DDSTOP IDDSTOP 4.75 4.0 0.1 5.0 8.0 0.2 5.25 14 50 5.0 110 5.25 200 V mA V V mA mV VLRRUN VLR STOP -- -- 20 10 150 100 mV VLRRUN VLDSTOP T PRE T SD T SD-T PRE -- -- 120 155 40 40 135 170 150 150 160 -- C C C 20 30 45 Notes 9. Specification with external capacitor 2.0 F< C < 10 F and 200 m ESR 10 . Capacitor value up to 47 F can be used. 10. Total VDD regulator current. A 5.0 mA current for current sense operational amplifier is included. Digital output supplied from VDD. 11. 12. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage specification. This parameter is guaranteed by process monitoring but not production tested 908E624 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, - 40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF) External Resistor Range Watchdog Period Accuracy with External Resistor (Excluding Resistor Accuracy) (13) LIN PHYSICAL LAYER LIN Transceiver Output Voltage Recessive State, TXD HIGH, IOUT = 1.0 A Dominant State, TXD LOW, 500 External Pullup Resistor Normal Mode Pullup Resistor to VSUP Stop, Sleep Mode Pullup Current Source Output Current Shutdown Threshold Leakage Current to GND VSUP Disconnected, VBUS at 18 V Recessive State, 8.0 V VSUP 18 V, 8.0 V VBUS 18 V, VBUS VSUP GND Disconnected, VGND = VSUP, VBUS at -18 V LIN Receiver Receiver Threshold Dominant Receiver Threshold Recessive Receiver Threshold Center Receiver Threshold Hysteresis V BUS_DOM V BUS_REC V BUS_CNT V BUS_HYS -- 0.6 0.475 -- -- -- 0.5 -- 0.4 -- 0.525 0.175 V LIN_REC V LIN_DOM R PU IPU IOV-CUR IBUS -- 0.0 -1.0 1.0 3.0 -- 10 20 1.0 VSUP VSUP -1 -- 20 -- 50 -- -- 30 2.0 75 -- 1.4 60 -- 150 k A mA A V REXT WDCACC 10 -15 -- -- 100 15 k % Symbol Min Typ Max Unit Notes 13. Watchdog timing period calculation formula: PWD = 0.991 * REXT + 0.648 (REXT in k and PWD in ms). 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, - 40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic HIGH-SIDE OUTPUTS HS1 AND HS2 Switch On Resistance TJ = 25C, ILOAD = 150 mA, VSUP > 9.0 V TJ = 125C, ILOAD = 150 mA, VSUP > 9.0 V TJ = 125C, ILOAD = 120 mA, 5.5 V < VSUP > 9.0 V Output Current Limit Overtemperature Shutdown Leakage Current Output Clamp Voltage IOUT = -100 mA HIGH-SIDE OUTPUT HS3 Switch On Resistance TJ = 25C, ILOAD = 50 m A, VSUP > 9.0 V TJ = 125C, ILOAD = 50 mA, VSUP > 9.0 V TJ = 125C, ILOAD = 30 mA, 5.5 V < VSUP > 9.0 V Output Current Limitation Overtemperature Shutdown (14), (15) Leakage Current ILIM THSSD ILEAK RDS(ON) -- -- -- 60 155 -- -- -- -- 100 -- -- 7.0 10 14 200 190 10 mA (14), (15) Symbol Min Typ Max Unit RDS(ON) -- -- -- ILIM THSSD ILEAK VCL - 6.0 -- -- 300 155 -- 2.0 -- 3.0 -- -- -- 2.5 4.5 -- 600 190 10 mA C A V C A Notes 14. This parameter is guaranteed by process monitoring but it is not production tested 15. When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI. 908E624 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, - 40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic CURRENT SENSE OPERATIONAL AMPLIFIER Rail-to-Rail Input Voltage Output Voltage Range Output Current 1.0 mA Output Current 5.0 mA Input Bias Current Input Offset Current Input Offset Voltage L1 AND L2 INPUTS Low Detection Threshold 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V High Detection Threshold 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V Hysteresis 5.5 V < VSUP < 27 V Input Current - 0.2 V < VIN < 40 V IIN -10 -- 10 VHYS 0.5 -- 1.3 A VTHH 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.5 4.7 V VTHL 2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.5 3.7 V V VOUT1 VOUT2 IB IO VIO 0.1 0.3 -- -100 - 25 -- -- -- -- -- VCC - 0.1 VCC - 0.3 250 100 25 nA nA mV VIMC - 0.1 -- VCC + 0.1 V V Symbol Min Typ Max Unit 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, - 40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic LIN PHYSICAL LAYER Driver Characteristics for Normal Slew Rate (16), (17) Dominant Propagation Delay TXD to LIN Dominant Propagation Delay TXD to LIN Recessive Propagation Delay TXD to LIN Recessive Propagation Delay TXD to LIN Propagation Delay Symmetry: t DOM-MIN - t REC-MAX Propagation Delay Symmetry: t DOM-MAX - t REC-MIN Driver Characteristics for Slow Slew Rate (16), (18) Dominant Propagation Delay TXD to LIN Dominant Propagation Delay TXD to LIN Recessive Propagation Delay TXD to LIN Recessive Propagation Delay TXD to LIN Propagation Delay Symmetry: t DOM-MIN - t REC-MAX Propagation Delay Symmetry: t DOM-MAX - t REC-MIN Driver Characteristics for Fast Slew Rate LIN High Slew Rate (Programming Mode) Receiver Characteristics and Wake-Up Timings Receiver Dominant Propagation Delay (19) Receiver Recessive Propagation Delay (19) Receiver Propagation Delay Symmetry Bus Wake-Up Deglitcher Bus Wake-Up Event Reported (20) Symbol Min Typ Max Unit t DOM-MIN t DOM-MAX t REC-MIN t REC-MAX dt1 dt2 -- -- -- -- -10.44 -- -- -- -- -- -- -- 50 50 50 50 -- 11 s s s s s s t DOM-MIN t DOM-MAX t REC-MIN t REC-MAX dt1s dt2s -- -- -- -- - 22 -- -- -- -- -- -- -- 100 100 100 100 -- 23 s s s s s s SRFAST -- 15 -- V / s t RL t RH t R-SYM t PROPWL t WAKE -- -- - 2.0 35 -- 3.5 3.5 -- -- 20 6.0 6.0 2.0 150 -- s s s s s Notes 16. VSUP from 7.0 V to 18 V, bus load R0 and C0 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. 17. See Figure 6, page 15. 18. See Figure 7, page 16. 19. Measured between LIN signal threshold VIL or VIH and 50% of RXD signal. 20. t WAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 8 and Figure 9, page 16. In Sleep mode the VDD rise time is strongly dependent upon the decoupling capacitor at VDD terminal. 908E624 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, - 40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic LIN PHYSICAL LAYER (CONTINUED) Output Current Shutdown Delay SPI INTERFACE TIMING SPI Operating Recommended Frequency L1 AND L2 INPUTS Wake-Up Filter Time (21) WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF) Watchdog Period External Resistor REXT = 10 k (1%) External Resistor REXT = 100 k (1%) Without External Resistor REXT (WDCONF Terminal Open) STATE MACHINE TIMING Reset Low-Level Duration after VDD High (25) Interrupt Low-Level Duration Normal Request Mode Timeout (25) Delay Between SPI Command and HS1 / HS2 / HS3 Turn On (22) , (23) Symbol Min Typ Max Unit tOV-DELAY -- 10 -- s f SPIOP 0.25 -- 4.0 MHz t WUF 8.0 20 38 s t PWD -- -- 97 10.558 99.748 150 -- -- 205 ms t RST t INT t NR TOUT t S-HSON t S-HSOFF t S-NR2N t W-SS , (23) 0.65 7.0 97 -- -- 6.0 1.0 10 150 3.0 3.0 35 1.35 13 205 10 10 70 ms s ms s s s s Delay Between SPI Command and HS1 / HS2 / HS3 Turn Off (22) Delay Between Normal Request and Normal Mode After W/ D Trigger Command (24) Delay Between SS Wake-Up (SS LOW to HIGH) and Normal Request Mode (VDD On and Reset High) Delay Between SS Wake-Up (SS LOW to HIGH) and First Accepted SPI Command Delay Between Interrupt Pulse and First SPI Command Accepted Minimum Time Between Two Rising Edges on SS Notes 21. 22. 23. 24. 25. 15 t W-SPI 90 t S-1STSPI t 2SS 30 15 40 80 s -- -- -- N/A N/A -- s s This parameter is guaranteed by process monitoring but is not production tested. Delay between turn-on or turn-off command and high-side on or high-side off, excluding rise or fall time due to external load. Delay between the end of the SPI command (rising edge of the SS) and start of device activation / deactivation. This parameter is guaranteed by process monitoring but it is not production tested. Also see Figure 10 on page 17 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS MICROCONTROLLER PARAMETRICS Table 4. Dynamic Electrical Characteristics (continued) All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, - 40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic CURRENT SENSE OPERATIONAL AMPLIFIER Supply Voltage Rejection Ratio (26) Common Mode Rejection Ratio Gain Bandwidth (26) Slew Rate Phase Margin (for Gain = 1, Load 100 pF / 5.0 k (26) Open Loop Gain (26) Symbol Min Typ Max Unit SVR CMR GBP SR PHMO OLG 60 70 1.0 0.5 40 -- -- -- -- -- -- 85 -- -- -- -- -- -- dB dB MHz V/ s dB Notes 26. This parameter is guaranteed by process monitoring but it is not production tested. MICROCONTROLLER PARAMETRICS Table 5. Microcontroller For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet. Module Core Timer Flash RAM ADC SPI ESCI Description High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz Two 16-Bit Timers with 2 Channels (TIM A and TIM B) 16 K Bytes 512 Bytes 10-Bit Analog-to-Digital Converter SPI Module Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud-Rate Adjustment Internal Clock Generation Module ICG 908E624 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS LIN, L1, and L2 Transient Pulse Generator 10 k 10k 1.0 nF 1nF Note Waveform in accordance with ISO7637 Part 1, Test Pulses 1, 2, 3a, and 3b. Figure 4. Test Circuit for Transient Test Pulses VSUP VSUP TXD LIN RXD R0 R0R0 and C0 combinations: and C0 Combinations: * 1.0 k and 1.0 nF - 1k Ohm and 1nF * 600 Ohm6.8 nF - 660 and and 6.8nF * 500 Ohm10 nF - 500 and and 10nF C0 Figure 5. Test Circuit for LIN Timing Measurements TXD LIN VLIN_REC tREC-MAX tDOM-MIN 58.1% VSUP 40% VSUP 28.4% VSUP tDOM-MAX tREC-MIN 74.4% VSUP 60% VSUP 42.2% VSUP RXD tRL tRH Figure 6. LIN Timing Measurements for Normal Slew Rate 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 15 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TXD LIN VLIN_REC tREC-MAX t DOM-MIN 61.6% VSUP 40% Vsup 25.1% VSUP t DOM-MAX tREC-MIN 77.8% VSUP 60% VSUP 38.9% VSUP RXD t RL t RH Figure 7. LIN Timing Measurements for Slow Slew Rate LIN VLIN_REC 0.4VSUP 0.4 VSUP Dominant level Dominant Level VDD t PROPWL TpropWL t WAKE Twake Figure 8. Wake-Up Sleep Mode Timing LIN VLIN_REC 0.4VSUP 0.4 VSUP Dominant level Dominant Level IRQ_A t PROPWL TpropWL tTwake WAKE Figure 9. Wake-Up Stop Mode Timing 908E624 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS VSUP VDD RST_A tRST tNRTOUT Figure 10. Power On Reset and Normal Request Time-out Timing 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 908E624 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E624 is well suited to perform relay control in applications like window lift, sunroof, etc., via a three-wire LIN bus. The device combines an HC908EY16 MCU core with flash memory together with a SmartMOS IC chip. The SmartMOS IC chip combines power and control in one chip. Power switches are provided on the SmartMOS IC configured as high-side outputs. Other ports are also provided, which include a current sense operational amplifier port and two wake-up terminals. An internal voltage regulator provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and one for ground. FUNCTIONAL TERMINAL DESCRIPTION See Figure 1, 908E624 Simplified Application Diagram, page 1, for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on page 3 for a depiction of the terminal locations on the package. PORT D I /O TERMINALS (PTD:0:1) PTD1/ TACH1 and PTD0/ TACH0/BEMF are specialfunction, bidirectional I /O port terminals that can also be programmed to be timer terminals. For details, refer to the 68HC908EY16 data sheet. PORT A I /O TERMINALS (PTA0:4) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0 : PTA4 are shared with the keyboard interrupt terminals KBD0 : KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/ SS terminal is likewise not accessible. For details, refer to the 68HC908EY16 data sheet. PORT E I /O TERMINAL (PTE1) PTE1/ RXD and PTE0/ TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/ TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally. For details, refer to the 68HC908EY16 data sheet. PORT B I/O TERMINALS (PTB1:7) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6 : PTB7 terminals are also shared with the Timer B module. The PTB0/AD0 and PTB2/AD2 terminals are not accessible in this device. For details, refer to the 68HC908EY16 data sheet. EXTERNAL INTERRUPT TERMINAL (IRQ) The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pullup resistor that is always activated, even when the IRQ terminal is pulled LOW. For details, refer to the 68HC908EY16 data sheet. EXTERNAL RESET TERMINAL (RST) A logic [0] on the RST terminal forces the MCU to a known startup state. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled LOW. Important To ensure proper operation, do not add any external pullup resistor. For details, refer to the 68HC908EY16 data sheet. PORT C I/O TERMINALS (PTC2:4) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2 : PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details, refer to the 68HC908EY16 data sheet. 908E624 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION MCU POWER SUPPLY TERMINALS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground terminals, respectively. The MCU operates from a singlepower supply. Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details, refer to the 68HC908EY16 data sheet. INTERRUPT TERMINAL (IRQ_A) IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. This terminal must be connected to the IRQ terminal of the MCU. WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF) This terminal is the configuration terminal for the internal watchdog. A resistor is connected to this terminal. The resistor value defines the watchdog period. If the terminal is open, the watchdog period is fixed to its default value. The watchdog can be disabled (e.g., for flash programming or software debugging) by connecting this terminal to GND. ADC SUPPLY TERMINALS (VDDA AND VSSA) VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground terminal for the ADC and should be tied to the same potential as EVSS via separate traces. For details, refer to the 68HC908EY16 data sheet. POWER SUPPLY TERMINALS (VSUP1 AND VSUP2) This VSUP1 power supply terminal supplies the voltage regulator, the internal logic, and LIN transceiver. This VSUP2 power supply terminal is the positive supply for the high-side switches. ADC REFERENCE TERMINALS (VREFL AND VREFH) VREFL and VREFH are the reference voltage terminals for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSSA via separate traces. For details, refer to the 68HC908EY16 data sheet. POWER GROUND TERMINAL (GND) This terminal is the device ground connection. HIGH-SIDE OUTPUT TERMINALS (HS1 AND HS2) These terminals are high-side switch outputs to drive loads such as relays or lamps. Each switch is protected with overtemperature and current limit (overcurrent). The output has an internal clamp circuitry for inductive load. The HS1 and HS2 outputs are controlled by SPI and have a direct enabled input (PWMIN) for PWM capability. TEST TERMINAL (FLSVPP) This terminal is for test purposes only. Do not connect in the application or connect to GND. HIGH-SIDE OUTPUT TERMINAL (HS3) This high-side switch can be used to drive small lamps, Hall-effect sensors, or switch pullup resistors. The switch is protected with overtemperature and current limit (overcurrent). The output is controlled only by SPI. PWMIN TERMINAL (PWMIN) This terminal is the direct PWM input for high-side outputs 1 and 2 (HS1 and HS2). If no PWM control is required, PWMIN must be connected to VDD to enable the HS1 and HS2 outputs. LIN BUS TERMINAL (LIN) The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. LIN TRANSCEIVER OUTPUT TERMINAL (RXD) This terminal is the output of LIN transceiver. The terminal must be connected to the microcontroller's Enhanced Serial Communications Interface (ESCI) module (RXD terminal). WAKE-UP TERMINALS (L1 AND L2) These terminals are high-voltage capable inputs used to sense external switches and to wake up the device from Sleep or Stop mode. During Normal mode the state of these terminals can be read through SPI. Important If unused these terminals should be connected to VSUP or GND to avoid parasitic transitions. In Low Power Mode this could lead to random wakeup events. RESET TERMINAL (RST_A) RST_A is the reset output terminal of the analog die and must be connected to the RST terminal of the MCU. Important To ensure proper operation, do not add any external pullup resistor. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION CURRENT SENSE OPERATIONAL AMPLIFIER TERMINALS (E+, E-, OUT, VCC) These are the terminals of the single-supply current sense operational amplifier. * The E+ and E- input terminals are the non-inverting and inverting inputs of the current sense operational amplifier, respectively. * The OUT terminal is the output terminal of the current sense operational amplifier. * The VCC terminal is the + 5.0 V single-supply connection. Note If the operational amplifier is not used, it is possible to connect all terminals (E+, E-, OUT and VCC) to GND - in this case all of the four terminals must be grounded. intended to supply the embedded microcontroller. The terminal is protected against shorts to GND with an integrated current limit (temperature shutdown could occur). Important The VDD, EVDD, VDDA, and VREFH terminals must be connected together. VOLTAGE REGULATOR AND CURRENT SENSE AMPLIFIER GROUND TERMINAL (AGND) The AGND terminal is the ground terminal of the voltage regulator and the current sense operational amplifier. Important GND, AGND, VSS, EVSS, VSSA, and VREFL terminals must be connected together. NO CONNECT TERMINALS (NC) The NC terminals are not connected internally. Note Each of the NC terminals can be left open or connected to ground (recommended). + 5.0 V VOLTAGE REGULATOR OUTPUT TERMINAL (VDD) The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is 908E624 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES 908E624 ANALOG DIE MODES OF OPERATION The 908E624 offers three operating modes: Normal (Run), Stop, and Sleep. In Normal mode the device is active and is operating under normal application conditions. The Stop and Sleep modes are low-power modes with wake-up capabilities. In Stop mode the voltage regulator still supplies the MCU with VDD (limited current capability) and in Sleep mode the voltage regulator is turned off (VDD = 0 V). Wake-up from Stop mode is initiated by a wake-up interrupt. Wakeup from Sleep mode is done by a reset and the voltage regulator is turned back on. The selection of the different modes is controlled by the MODE1:2 bits in the SPI Control register. Figure 11 describes how transitions are done between the different operating modes and Table 6, page 22, gives an overview of the operating mode. Normal Request Timeout Expired(NRTOUT) ) Normal Request timeout expired (t NRTOUT VDD Low VDD Low VDD High and Power Down Power Up Reset Reset Delay (t RST) Expired VDD High and Reset Delay (tRST) expired Normal Request WDdisabled WD Disabled WD Trigger WD trigger VDDLow Low V DD WD Failed WD failed VDDLow (>NRTOUT) expired) Expired VDD LOW (>t NRTOUT and and LVF = 0 VSUV = 0 Normal Stop Command STOP Command Sleep Command SLEEP Command Wake-Up (Reset) Wake-Up (Reset) Sleep Stop VDD Low VDD Low Legend WD: Watchdog Notes: WD Disabled: Watchdog disabled (WDCONF terminal connected to GND) WD - means Watchdog WD Trigger: Watchdog is triggered by SPI command WD Failed:WD disabled - trigger or trigger occurs in closed window No watchdog means Watchdog disabled (WDCONF terminal connected to GND) WD trigger - means Watchdog is triggered by SPI command Stop Command: Stop command sent via SPI WD failed - means no Watchdog trigger or trigger occurs in closed window Sleep Command: Sleep command sent via SPI STOP Command - means STOP command sent via SPI Wake-Up: L1 or L2 state change or LIN bus wake-up or SS rising edge SLEEP Command - means SLEEP command send via SPI Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge Figure 11. Operating Modes and Transitions Wake-Up Interrupt Wake-Up Interrupt 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 6. Operating Modes Overview Device Mode Reset Normal Request Normal (Run) Stop Voltage Regulator VDD ON VDD ON VDD ON VDD ON with limited current capability VDD OFF Wake-Up Capabilities N/A N/A N/A LIN wake-up, L1, L2 state change, SS rising edge LIN wake-up L1, L2 state change RST_A Output LOW HIGH HIGH HIGH Watchdog Function Disabled 150 ms time out if WD enabled Window WD if enabled Disabled HS1, HS2, and HS3 Disabled Enabled Enabled Disabled LIN Interface Recessive only Transmit and receive Transmit and receive Recessive state with wake-up capability Recessive state with wake-up capability Sense Amplifier Not active Not active Active Not active Sleep LOW Disabled Disabled Not active INTERRUPTS In Normal (Run) mode the 908E624 has four different interrupt sources. An interrupt pulse on the IRQ_A terminal is generated to report a fault to the MCU. All interrupts are not maskable and cannot be disabled. After an Interrupt the INTSRC bit in the SPI Status register is set, indicating the source of the event. This interrupt source information is only transferred once, and the INTSRC bit is cleared automatically. Low-Voltage Interrupt Wake-Up Interrupts In Stop mode the IRQ_A terminal reports wake-up events on the L1, L2, or the LIN bus to the MCU. All wake-up interrupts are not maskable and cannot be disabled. After a wake-up interrupt, the INTSRC bit in the Serial Peripheral Interface (SPI) Status register is set, indicating the source of the event. This wake-up source information is only transferred once, and the INTSRC bit is cleared automatically. Figure 12, page 23, describes the Stop / Wake-Up procedure. Voltage Regulator Temperature Prewarning (VDDT) Low-voltage interrupt (LVI) is related to external supply voltage VSUP1. If this voltage falls below the LVI threshold, it will set the LVF bit in the SPI Status register and an interrupt will be initiated. The LVF bit remains set as long as the Lowvoltage condition is present. During Sleep and Stop mode the low-voltage interrupt circuitry is disabled. High-Voltage Interrupt Voltage regulator temperature prewarning (VDDT) is generated if the voltage regulator temperature is above the TPRE threshold. It will set the VDDT bit in the SPI Status register and an interrupt will be initiated. The VDDT bit remains set as long as the error condition is present. During Sleep and Stop mode the voltage regulator temperature prewarning circuitry is disabled. High-Side Switch Thermal Shutdown (HSST) High-voltage interrupt (HVI) is related to external supply voltage VSUP1. If this voltage rises above the HVI threshold, it will set the HVF bit in the SPI Status register and an interrupt will be initiated. The HVF bit remains set as long as the high-voltage condition is present. During Sleep and Stop mode the high-voltage interrupt circuitry is disabled. The high-side switch thermal shutdown HSST is generated if one of the high-side switches HS1 : HS3 is above the HSST threshold, it will shutdown all high-side switches, set the HSST flag in the SPI Status register and an interrupt will be initiated. The HSST bit remains set as long as the error condition is present. During Sleep and Stop mode the high-side switch thermal shutdown circuitry is disabled. 908E624 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES MCU From Reset Power Die initialize operate SPI: 2x STOP Command Switch to VREG low current mode STOP Wake Up on LIN or L1, L2? IRQ interrupt ? Assert IRQ SPI: reason for interrupt Switch to VREG high current mode operate Figure 12. Stop Mode / Wake-Up Procedure 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES ANALOG DIE INPUTS / OUTPUTS High-Side Output Terminals HS1 and HS2 HS3) are turned off and latched off. The failure is reported by the HSST bit in the SPI Control register. Sleep and Stop Mode These are two high-side switches used to drive loads such as relays or lamps. They are protected with overtemperature and current limit (overcurrent) and include an active internal clamp circuitry for inductive load drive. Control is done using the SPI Control register. PWM capability is offered through the PWMIN input terminal. The high-side switch is turned on if both the HSxON bit in the SPI Control register is set and the PWMIN input is HIGH (refer to Figure 13, page 24). In order to have HS1 on, the PWMIN must be HIGH and bit HS1ON must be set. The same applies to the HS2 output. If no PWM control is required, PWMIN must be connected to the VDD terminal. Current Limit (Overcurrent) Protection In Sleep and Stop modes the high-sides are disabled. High-Side Output HS3 This high-side switch can be used to drive small lamps, Hall-effect sensors, or switch pullup resistors. Control is done using the SPI Control register. No direct PWM control is possible on this terminal (refer to Figure 14, page 25). Current Limit (Overcurrent) Protection This high-side feature switch feature current limit to protect it against overcurrent and short circuit conditions. Overtemperature Protection These high-side switches feature current limit to protect them against overcurrent and short circuit conditions. Overtemperature Protection If an overtemperature condition occurs on any of the three high-side switches, all high-side switches (HS1, HS2 and HS3) are turned off and latched off. The failure is reported by the HSST bit in the SPI Control register. Sleep and Stop Mode If an overtemperature condition occurs on any of the three high-side switches, all high-side switches (HS1, HS2 and . In Sleep and Stop mode the high-side is disabled. PWMIN VSUP2 MODE1:2 On/Off HSxON High-Side Driver Charge Pump, Current Limit Protection, Overtemperature Protection HSx Control Status Figure 13. High-Side HS1 and HS2 Circuitry 908E624 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES . MODE1:2 VSUP2 On/Off HS3ON High-Side Driver Charge Pump, Current Limit Protection, Overtemperature Protection HS3 Control Status Figure 14. High-Side HS3 Circuitry LIN PHYSICAL LAYER The LIN bus terminal provides a physical layer for singlewire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low-side MOSFET with over current protection and thermal shutdown. An internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The slew rate can be selected for optimized operation at 10 and 20kBit/s as well as a fast baud rate for test and programming. The slew rate can be adapted with the bits LINSL2:1 in the SPI Control Register. The initial slew rate is optimized for 20kBit/s. The LIN terminal offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled in Normal and Normal Request mode. An over current condition (e.g. LIN bus short to Vbat) or a over temperature in the output low-side FET will shutdown the transmitter and set the LINFAIL flag in the SPI Status Register. For improved performance and safe behavior in case of LIN bus short to Ground or LIN bus leakage during low power mode the internal pull-up resistor on the LIN terminal can be disconnected, with the LIN-PU bit in the SPI Control Register, and a small current source keeps the LIN bus at recessive level. In case of a LIN bus short to GND, this feature will reduce the current consumption in STOP and SLEEP modes. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES MODE2:1 LINSL2:1 LIN-PU VSUP1 LINWU LINFAIL Control 2A 30k LIN bus TXD Slope Control WakeUp Filter GND RXD Figure 15. LIN Interface TXD Terminal Receiver The TXD terminal is the MCU interface to control the state of the LIN transmitter (see Figure 2, page 2). When TXD is LOW, the LIN terminal is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off (recessive state). The TXD terminal has an internal pullup current source in order to set the LIN bus to recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. RXD Terminal the Stop mode sequence the internal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN terminal in recessive state. The receiver is still active and able to detect wake-up events on the LIN bus line. A dominant level longer than TpropWL followed by an rising edge will generate a wake-up interrupt and set the LINWF flag in the SPI Status Register. Also see Figure 9, page 16. SLEEP Mode and Wake-up Feature The RXD transceiver terminal is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. STOP Mode and Wake-up Feature During STOP mode operation the transmitter of the physical layer is disabled. In case the bit LIN-PU was set in During SLEEP mode operation the transmitter of the physical layer is disabled. In case the bit LIN-PU was set in the Sleep mode sequence the internal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN terminal in recessive state. The receiver is still active to be able to detect wake-up events on the LIN bus line. A dominant level longer than TpropWL followed by an rising edge will generate a system wake-up (reset) and set the LINWF flag in the SPI Status Register . Also see Figure 8, page 16). 908E624 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES WINDOW WATCHDOG The window watchdog is configurable using an external resistor at the WDCONF terminal. The watchdog is cleared through by the MODE1:2 bits in the SPI Control register (refer to Table 8, page 29). A watchdog clear is only allowed in the open window. If the watchdog is cleared in the closed window or has not been cleared at the end of the open window, the watchdog will generate a reset on the RST_A terminal and reset the whole device. Note The watchdog clear in Normal request mode (150 ms) (first watchdog clear) has no window. Overtemperature Protection The voltage regulator also features an overtemperature protection having an overtemperature warning (Interrupt VDDT) and an overtemperature shutdown. Stop Mode During Stop mode, the Stop mode regulator supplies a regulated output voltage. The Stop mode regulator has a limited output current capability. Sleep Mode In Sleep mode the voltage regulator external VDD is turned off. Window closed no watchdog clear allowed Window open for watchdog clear FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E624, various parameters (e.g., ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the "empty" (0xFF) state: * 0xFD80 :0xFDDF Trim and Calibration Values * 0xFFFE : 0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values WD timing x 50% WD timing x 50% WD period (tPWD) (PWD) WD timing selected by resistor on WDCONF terminal. Figure 16. Window Watchdog Operation Watchdog Configuration If the WDCONF terminal is left open, the default watchdog period is selected (typ. 150 ms). If no watchdog function is required, the WDCONF terminal must be connected to GND. The watchdog period is calculated using the following formula: t PWD [ms] = 0.991 * REXT [k] + 0.648 The usage of the trim values, located in the flash memory, is explained in the following. Internal Clock Generator (ICG) Trim Value VOLTAGE REGULATOR The 908E624 chip contains a low-power, low dropout voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts an unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller. Current Limit (Overcurrent) Protection The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low-frequency base clock (IBASE), will vary as much as 25 percent due to process, temperature, and voltage dependencies. To compensate for these dependencies, an ICG trim value is located at address $FDC2. After trimming the ICG, a range of typ. 2% (3% max.) at nominal conditions (filtered (100nF) and stabilized (4,7uF) VDD = 5V, TAmbient~23C) and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 data sheet. To trim the ICG, these values have to be copied to the ICG Trim Register ICGTR at address $38 of the MCU. Important The value has to be copied after every reset. The voltage regulator has current limit to protect the device against overcurrent and short circuit conditions. OPERATING MODES OF THE MCU For a detailed description of the operating modes of the MCU, refer to the MC68HC908EY16 data sheet. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS 908E624 SPI INTERFACE AND CONFIGURATION The serial peripheral interface creates the communication link between the microcontroller and the analog die of the 908E624. The interface consists of four terminals (see Figure 17): * SS -- Slave Select * MOSI -- Master-Out Slave-In * MISO -- Master-In Slave-Out * SPSCK -- Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 8 bits of control information and the slave replies with 8 bits of status data. SS Register write data MOSI D7 D6 D5 D4 D3 D2 D1 D0 Register read data MISO D7 D6 D5 D4 D3 D2 D1 D0 SPSCK Read data latch Write data latch Rising edge of SPSCK Change MISO/MOSI Output Falling edge of SPSCK Sample MISO/MOSI Input Figure 17. SPI Protocol During the inactive phase of the SS (HIGH), the new data The data transfer is only valid if exactly 8 sample clock transfer is prepared. edges are present in the active (low) phase of SS. The falling edge of the SS indicates the start of a new data The rising edge of the slave select SS indicates the end of transfer and puts the MISO in the low-impedance state and the transfer and latches the write data (MOSI) into the latches the analog status data (Register read data). register The SS high forces MISO to the high impedance state. With the rising edge of the SPI clock, SPSCK the data is moved to MISO/MOSI terminals. With the falling edge of the SPI clock SPSCK the data is sampled by the Receiver. 908E624 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS SPI REGISTER OVERVIEW Table 7 summarizes the SPI Register bit meaning, reset value, and bit reset condition. . Table 7. SPI Register Overview Read / Write Information Write Read Write Reset Value Write Reset Condition 0 POR, RESET Bit D7 LINSL2 INTSRC (27) D6 LINSL1 LINWU or LINFAIL 0 POR, RESET D5 LIN-PU HVF D4 HS3ON LVF or BATFAIL (28) 0 POR, RESET D3 HS2ON VDDT D2 HS1ON HSST D1 MODE2 L2 D0 MODE1 L1 0 POR 0 POR, RESET 0 POR, RESET -- -- -- -- Notes 27. D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source. 28. The first SPI read after reset returns the BATFAIL flag state on bit D4. SPI Control Register (Write) Table 8 shows the SPI Control register bits by name. Table 8. Control Bits Function (Write Operation) an erroneous short of the LIN bus to ground this will significantly reduce the power consumption, e.g. in combination with STOP/SLEEP mode. HS3ON : HS1ON -- High-Side H3 : HS1 Enable Bits D7 D6 D5 D4 D3 D2 D1 D0 LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1 LINSL2 : 1 -- LIN Baud Rate and Low-Power Mode Selection Bits These bits enable the HSx. Reset clears the HSxON bit. * 1 = HSx switched on (refer to Note below). * 0 = HSx switched off. Note If no PWM on HS1 and HS2 is required, the PWMIN terminal must be connected to the VDD terminal. MODE2 : 1 -- Mode Section Bits These bits select the LIN slew rate and requested lowpower mode in accordance with Table 9. Reset clears the LINSL2 : 1 bits. Table 9. LIN Baud Rate and Low-Power Mode Selection Bits LINSL2 0 0 1 1 LINSL1 0 1 0 1 Description Baud Rate up to 20 kbps (normal) Baud Rate up to 10 kbps (slow) Fast Program Download Baud Rate up to 100 kbps Low-Power Mode (Sleep or Stop) Request The MODE2 : 1 bits control the operating modes and the watchdog in accordance with Table 10. Table 10. Mode Selection Bits MODE2 0 0 1 1 MODE1 0 1 0 1 Description Sleep Mode (29) Stop Mode (29) Watchdog Clear (30) Run (Normal) Mode LIN-PU -- LIN Pullup Enable Bit This bit controls the LIN pullup resistor during Sleep and Stop modes. * 1 = Pullup disconnected in Sleep and Stop modes. * 0 = Pullup connected in Sleep and Stop modes. In case the Pullup is disconnected a small current source is used to pull the LIN terminal in recessive state. In case of Notes 29. To enter Sleep and Stop mode, a special sequence of SPI commands is implemented. 30. The device stays in Run (Normal) mode. To safely enter Sleep or Stop mode and to ensure that these modes are not affected by noise issue during SPI transmission, the Sleep / Stop commands require two SPI transmissions. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Sleep Mode Sequence The Sleep command, as shown in Table 11, must be sent twice. Table 11. Sleep Command Bits LINSL2 LINSL1 1 1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1 0/1 0 0 0 0 0 Stop Mode Sequence The Stop command, as shown in Table 12, must be sent twice. Table 12. Stop Command Bits LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1 1 1 0/1 0 0 0 0 1 SPI Status Register (Read) Table 13 shows the SPI Status register bits by name. Table 13. Control Bits Function (Read Operation) D7 INTSRC D6 LINWU or LINFAIL D5 HVF D4 LVF or BATFAIL D3 VDDT D2 HSST D1 L2 D0 L1 INTSCR -- Register Content Flags or Interrupt Source This bit indicates if the register contents reflect the flags or an interrupt / wake-up interrupt source. * 1 = D6 : D0 reflects the interrupt or wake-up source. * 0 = No interrupt occurred. Other SPI bits report real time status. LINWU / LINFAIL -- LIN Status Flag Bit * 1 = Low-voltage condition has occurred. * 0 = No low-voltage condition. VDDT -- Voltage Regulator Status Flag Bit This bit indicates a LIN wake-up condition. * 1 = LIN bus wake-up occurred or LIN overcurrent/ overtemperature occurred. * 0 = No LIN bus wake-up occurred. In case of a LIN overcurrent/overtemperature condition the LIN transmitter is disabled. To reenable the LIN transmitter, the error condition must be GONE and the LINWU/LINFAIL flag must be cleared. The flag is cleared by reading the flag when it is set (SPI command). HVF -- High-Voltage Flag Bit This flag is set as pre-warning in case of an overtemperature condition on the voltage regulator. * 1 = Voltage regulator overtemperature condition, prewarning. * 0 = No overtemperature detected. HSST -- High-Side Status Flag Bit This flag is set on overtemperature conditions on one of the high-side outputs. * 1 = HSx off due to overtemperature. * 0 = No overtemperature. In case one of the high-sides has an overtemperature condition all high-side switches are disabled. To reenable the high-side switches, the flags have to be cleared, by reading the flag when it is set and by writing a one to high-side HSxON bit (two SPI commands are necessary). L2:L1-- Wake-Up Inputs L1, L2 Status Flag Bit This flag is set on an overvoltage (VSUP1) condition. * 1 = High-voltage condition has occurred. * 0 = no High-voltage condition. LVF / BATFAIL -- Low-Voltage Flag Bit This flag is set on an undervoltage (VSUP1) condition. These flags reflect the status of the L2 and L1 input terminals and indicate the wake-up source. * 1 = L2 : L1 input high or wake-up by L2 : L1 (first register read after wake-up indicated with INTSRC = 1). * 0 = L2 : L1 input low. 908E624 30 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS TYPICAL APPLICATIONS DEVELOPMENT SUPPORT As the 908E624 has the MC68HC908EY16 MCU embedded typically all the development tools available for the MCU also apply for this device, however due to the fact of the additional analog die circuitry and the nominal +12 V supply voltage some additional items have to be considered: * nominal 12 V rather than 5.0 V or 3.0 V supply * high voltage VTST might be applied not only to IRQ terminal, but IRQ_A terminal * MCU monitoring (Normal request timeout) has to be disabled For a detailed information on the MCU related development support see the MC68HC908EY16 data sheet section development support. The programming is principally possible at two stages in the manufacturing process -- first on chip level, before the IC is soldered onto a PCB board and second after the IC is soldered onto the PCB board. Chip Level Programming On Chip level the easiest way is to only power the MCU with +5.0 V (see Figure 18) and not to provide the analog chip with VSUP, in this setup all the analog terminal should be left open (e.g. VSUP[1:2]) and interconnections between MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well described in the MC68HC908EY16 data sheet - section development support. VSUP[1:2] GND VDD AGND +5V VREFH RST RST_A VDD VDDA EVDD 100nF 4.7F 1 1F + 3 4 1F + 5 C1+ VCC 16 + 1F 1F + VDD + 1F 74HC125 10k 5 4 3 1 VTST IRQ MM908E624 VREFL VSSA EVSS C1C2+ GND V+ 15 2 6 IRQ_A 10k PTB4/AD4 CLK PTC4/OSC1 10k PTA1/KBD1 DATA 10k PTA0/KBD0 PTB3/AD3 WDCONF +5V RS232 DB-9 2 3 5 C2- MAX232 V- 9.8304MHz CLOCK 7 T2OUT 8 R2IN T2IN 10 74HC125 R2OUT 9 2 6 Figure 18. Normal Monitor Mode Circuit (MCU only) Of course it is also possible to supply the whole system with VSUP (12 V) instead as described in Figure 19, page 32. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 31 TYPICAL APPLICATIONS PCB Level Programming If the IC is soldered onto the PCB board it is typically not possible to separately power the MCU with +5.0 V, the whole system has to be powered up providing VSUP (see Figure 19). VDD VSUP 47F + 100nF VSUP[1:2] GND VDD AGND VREFH RST RST_A VDD 100nF 1 1F + 3 4 1F + 5 C2C1C2+ GND V+ 15 2 6 1F 74HC125 7 T2OUT 8 R2IN T2IN 10 74HC125 3 5 R2OUT 9 2 1 3 6 4 5 10k DATA PTA0/KBD0 + VDD + C1+ VCC 16 + 1F 1F IRQ_A 10k PTB4/AD4 CLK PTC4/OSC1 10k PTA1/KBD1 10k PTB3/AD3 WDCONF VDD VTST 2.2k IRQ 4.7F VREFL VSSA EVSS VDDA EVDD MM908E624 MAX232 V- 9.8304MHz CLOCK RS232 DB-9 2 Figure 19. Normal Monitor Mode Circuit Table 14 summarizes the possible configurations and the necessary setups. Table 14. Monitor Mode Signal Requirements and Options Serial Communication PTA0 PTA1 Mode Selection ICG PTB3 PTB4 COP Communication Speed Normal Request Bus Timeout External Frequenc Baud Rate Clock y disabled disabled disabled 9.8304 MHz 9.8304 MHz -- 2.4576 MHz 2.4576 MHz Nominal 1.6MHz Nominal 1.6MHz 9600 9600 Nominal 6300 Nominal 6300 Mode IRQ RST WDCONF Reset Vector Normal Monitor VTST VDD VDD GND X 1 0 0 1 OFF OFF disabled disabled disabled Forced Monitor VDD GND GND $FFFF (blank) 1 0 X X ON User VDD VDD REXT not $FFFF (not blank) X X X X ON enabled enabled -- Notes 31. PTA0 must have a pullup resistor to VDD in monitor mode. 32. 33. 34. 35. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256. X = don't care. VTST is a high voltage VDD + 3.5 V VTST VDD + 4.5 V. 908E624 32 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS EMC/EMI RECOMMENDATIONS This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be e.g. found on the Freescale website www.freescale.com. VSUP Terminals (VSUP1 and VSUP2) MCU Digital Supply Terminals (EVDD and EVSS) Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. MCU Analog Supply Terminals (VREFH, VDDA and VREFL, VSSA) Its recommended to place a high-quality ceramic decoupling capacitor close to the VSUP terminals to improve EMC/EMI behavior. LIN Terminal For DPI (Direct Power Injection) and ESD (Electro Static Discharge) it is recommended to place a high-quality ceramic decoupling capacitor near the LIN terminal. An additional varistor will further increase the immunity against ESD. A ferrite in the LIN line will suppress some of the noise induced. Voltage Regulator Output Terminals (VDD and AGND) To avoid noise on the analog supply terminals it is important to take special care on the layout. The MCU digital and analog supplies should be tied to the same potential via separate traces and connected to the voltage regulator output. Figure 20 and Figure 21 show the recommendations on schematics and layout level and Table 15 indicates recommended external components and layout considerations. Use a high-quality ceramic decoupling capacitor to stabilize the regulated voltage. D1 VSUP C1 + C2 VSUP1 VSUP2 VDD AGND VREFH L1 LIN V1 C5 C3 C4 VREFL VSSA EVSS LIN EVDD VDDA MM908E624 GND Figure 20. EMC/EMI recommendations 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 33 TYPICAL APPLICATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 VREFH 48 VDDA 47 EVSS 45 VSSA 44 VREFL 43 42 EVDD 46 908E624 41 40 39 38 37 36 35 AGND 34 VDD 33 NC 32 C3 Comment: Terminal 32 NC - used for signal routing C4 VSUP1 31 LIN 29 VSUP2 28 C1 GND 30 C2 D1 L1 V1 VBAT LIN C5 Figure 21. PCB Layout Recommendations . Table 15. Component Value Recommendation Component D1 C1 C2 C3 Bulk Capacitor 100 nF, SMD Ceramic 100 nF, SMD Ceramic Close (<5 mm) to VSUP1, VSUP2 terminals with good ground return Close (<3 mm) to digital supply terminals (EVDD, EVSS) with good ground return. The positive analog (VREFH, VDDA) and the digital (EVDD) supply should be connected right at the C3. C4 C5 4.7 F, SMD Ceramic or Low ESR 180 pF, SMD Ceramic Bulk Capacitor Close (<5 mm) to LIN terminal. Total Capacitance per LIN node has to be below 220 pF. (Ctotal = CLIN-Terminal + C5 + CVaristor ~ 10 pF + 180 pF + 15 pF) V1(37) L1(37) Varistor Type TDK AVR-M1608C270MBAAB SMD Ferrite Bead Type TDK MMZ2012Y202B Optional (close to LIN connector) Optional, (close to LIN connector) Recommended Value(36) Comments / Signal routing Reverse battery protection Notes 36. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer's responsibility to validate their application. 37. Components are recommended to improve EMC and ESD performance. 908E624 34 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGING DIMENSIONS PACKAGING PACKAGING DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number below. 10.3 7.6 7.4 5 C 9 B 2.65 2.35 52X 1 54 0.65 PIN 1 INDEX 4 9 B B 18.0 17.8 C L 27 28 5.15 2X 27 TIPS A 54X SEATING PLANE 0.3 ABC 0.10 A NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. (0.29) A 0.30 0.25 6 A 0.13 0.38 0.22 M BASE METAL R0.08 MIN (0.25) 0.25 GAUGE PLANE PLATING 0 MIN 0.29 0.13 A BC 8 ROTATED 90 CLOCKWISE SECTION A-A 8 0 0.9 0.5 SECTION B-B DWB SUFFIX EW SUFFIX (Pb-FREE) CASE 1365-01 54-TERMINAL SOIC WIDE BODY ISSUE O PLASTIC PACKAGE 98ASA99294D ISSUE O DATE 09/19/01 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 35 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0) ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0) INTRODUCTION This thermal addendum is provided as a supplement to the MM908E624 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet. Packaging and Thermal Considerations 908E624 54-TERMINAL SOICW The MM908E624 is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn. For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RJ21 and RJ22, respectively. TJ1 TJ2 RJA11 RJA12 RJA21 RJA22 . DWB SUFFIX EW (Pb-FREE) SUFFIX 98ASA99294D 54-TERMINAL SOICW = P1 P2 Note For package dimensions, refer to the MM908E624 datasheet. The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below Standards Table 16. Thermal Performance Comparison 1 = Power Chip, 2 = Logic Chip [C/ W] Thermal Resistance RJAmn (1)(2) RJBmn (2)(3) m = 1, n=1 40 25 57 21 m = 1, n = 2 m = 2, n = 1 31 16 47 12 m = 2, n=2 36 21 52 16 RJAmn (1)(4) RJCmn (5) Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, "infinite" heat sink attached to exposed pad. 54 Terminal SOIC 0.65 mm Pitch 17.9 mm x 7.5 mm Body 908E624 36 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0) A PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST PTB1/AD1 PTD0/TACH0 PTD1/TACH1 NC NC NC PWMIN RST_A IRQ_A NC NC NC L1 L2 HS3 HS2 HS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD NC RXD WDCONF +E -E OUT VCC AGND VDD NC VSUP1 GND LIN VSUP2 908E624 Terminal Connections 54-Terminal SOICW 0.65 mm Pitch 17.9 mm x 7.5 mm Body Figure 22. Surface Mount for SOIC Wide Body non-Exposed Pad Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air Table 17. Thermal Resistance Performance 1 = Power Chip, 2 = Logic Chip (C/W) Terminal Resistance RJAmn Area A (mm2) 0 300 600 m = 1, n=1 58 56 54 m = 1, n = 2 m = 2, n = 1 48 46 45 m = 2, n=2 53 51 50 Outline: Area A: Ambient Conditions: RJAmn is the thermal resistance between die junction and ambient air. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 37 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0) 70 Thermal Resistance [C/W] 60 50 40 30 20 10 0 RJA11 R JA x 0 JA11 RJA22 RJA22 RJA12 = RJA21 RJA12=RJA21 Heat spreading area A [mm] 300 600 Figure 23. Device on Thermal Test Board 100 Thermal Resistance [C/W] 10 1 x RJA11 RJA22 RJA12 = RJA21 0.1 1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time[s] Figure 24. Transient Thermal Resistance RJA (1.0 W Step Response) Device on Thermal Test Board Area A = 600 (mm2) 908E624 38 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION 7.0 DATE 5/2006 DESCRIPTION OF CHANGES * * * * * * * * * * * * * Implemented Revision History page Added Pb-Free package option (Suffix EW) and higher Soldering temperature Added "Y" temperature (TJ - 40C to 125C) code option (MM908E624AYEW) and updated condition statement for Static and Dynamic Electrical Characteristics Corrected Figure 11, Operating Modes and Transitions ("STOP command" for transition from Normal to Stop state) Updated Figure 21, PCB Layout Recommendations, comment NC Terminal used for signal routing Updated Table 15, Component Value Recommendation Corrected Figure 23, Device on Thermal Test Board Removed reference to Note 11, Voltage Regulator - Dropout Voltage Added comment "LIN in recessive state" to Supply Current Range in Stop Mode and Sleep Mode Updated format to match current data sheet standard. Added Figure 10, Power On Reset and Normal Request Time-out Timing Added LIN P/L details Made clarifications on Max Ratings Table for TA and TJ Thermal Ratings and the accompanying Note Removed "Advance Information" watermark from first page. 8.0 3/2007 * 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 39 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2006. All rights reserved. MM908E624 Rev. 8.0 3/2007 |
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